Common source amp with diode connected load #354
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Common source amplifier with diode connected load NMOS are used for both input and load devices.
…mplifier_diodeconnectedload
common source amplifier with diode connected load
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Thank you for the PR @hirunisilva275 . Please include DRC and LVS reports to confirm the design is clean. |
| mtop = multipliers if subckt_only else 1 | ||
| model = pdk.models[n_or_p_fet] | ||
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| source_netlist = """.subckt {circuit_name} {nodes} """ + f'l={length} w={width} m={mtop} ' + """ |
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You don't need to write the spice for the netlist, you can construct it using the sub-devices. Refer to
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Okay so we need only the pcell for that? I am a bit confused. can you explain further.
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The common source amp uses subdevices such as nmos. Each of those devices have their own netlists. You can directly connect those netlists using python code to make the netlist for the CS amp. You don't need to write any spice, just instantiate the subdevices in glayout and connect them.
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This is another, probably better example.
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| instance_format = "X{name} {nodes} {circuit_name} l={length} w={width} m={mult}" | ||
| return Netlist( | ||
| circuit_name='CMIRROR', |
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The name of the component is not cmirror right?
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No I am working on the common source amplifier with diode connected load. I am still working on the DRC and LVS. I will be able to update the PR soon with the new results.
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Hello Harsha,
Thank you for the response.
from glayout.flow.routing.straight_route import straight_route
from glayout.flow.routing.c_route import c_route
def csamplifier_diodeconnectedload(pdk: MappedPDK):
csamplifier_diodeconnectedloadComp = Component()
nfet_in = nmos(pdk, with_substrate_tap=False, with_dummy=(False, False))
nfet_load = nmos(pdk, with_substrate_tap=False, with_dummy=(False, True))
cin_ref = csamplifier_diodeconnectedloadComp << nfet_in
cload_ref = csamplifier_diodeconnectedloadComp << nfet_load
cin_ref.movex(evaluate_bbox(nfet_load)[0] + pdk.util_max_metal_seperation
())
csamplifier_diodeconnectedloadComp << c_route(pdk, cload_ref.ports[
"multiplier_0_gate_W"], cload_ref.ports["multiplier_0_drain_W"])
#csamplifier_diodeconnectedloadComp << straight_route(pdk,
cin_ref.ports["multiplier_0_gate_E"],
cload_ref.ports["multiplier_0_gate_E"])
csamplifier_diodeconnectedloadComp << c_route(pdk, cin_ref.ports[
"multiplier_0_drain_E"], cload_ref.ports["multiplier_0_source_E"])
return csamplifier_diodeconnectedloadComp
csamplifier_diodeconnectedload(sky130).write_gds(
"csamplifier_diodeconnectedload.gds")
display_gds("csamplifier_diodeconnectedload.gds", scale=5)
So I can do like this and then do the DRC?
Best Regards,
*Nimasha Hiruni Silva*
Graduate Research Assistant
Florida International University
…On Thu, Dec 12, 2024 at 1:53 PM Harsh Khandeparkar ***@***.***> wrote:
***@***.**** commented on this pull request.
------------------------------
In
openfasoc/generators/glayout/glayout/flow/blocks/composite/commonsourceampwithdiodeconnctedload/commonsourceamp_diodeconnectedload.py
<#354 (comment)>:
> +def csamplifier_diodeconnectedload_netlist(
+ pdk: MappedPDK,
+ width: float,
+ length: float,
+ multipliers: int,
+ n_or_p_fet: Optional[str] = 'nfet',
+ subckt_only: Optional[bool] = False
+ ) -> Netlist:
+ if length is None:
+ length = pdk.get_grule('poly')['min_width']
+ if width is None:
+ width = 3
+ mtop = multipliers if subckt_only else 1
+ model = pdk.models[n_or_p_fet]
+
+ source_netlist = """.subckt {circuit_name} {nodes} """ + f'l={length} w={width} m={mtop} ' + """
This
<https://github.com/idea-fasoc/OpenFASOC/blob/e7f461123dd9e95216ac9cd59f057c8922fe47de/openfasoc/generators/glayout/glayout/flow/blocks/composite/diffpair_cmirror_bias/diff_pair_cmirrorbias.py#L41-L61>
is another, probably better example.
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Sorry for the late reply, but can you elaborate your question? |
Common source amp with diode connected load